Integrated Circuit Package and Method

ABSTRACT

In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

PRIORITY CLAIM AND CROSS REFERENCE

This application is a divisional of U.S. patent application Ser. No. 16/745,991, filed on Jan. 17, 2020, which application is hereby incorporated herein by reference.

BACKGROUND

As semiconductor technologies continue to evolve, integrated circuit dies are becoming increasingly smaller. Further, more functions are being integrated into the dies. Accordingly, the numbers of input/output (I/O) pads needed by dies has increased while the area available for the I/O pads has decreased. The density of the I/O pads has risen quickly over time, increasing the difficulty of die packaging.

In some packaging technologies, integrated circuit dies are singulated from wafers before they are packaged. An advantageous feature of this packaging technology is the possibility of forming fan-out packages, which allow the I/O pads on a die to be redistributed to a greater area. The number of I/O pads on the surfaces of the dies may thus be increased.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 through 25 are cross-sectional views of intermediate steps during a process for forming a package component, in accordance with some embodiments.

FIG. 26 illustrates a system including a package component, in accordance with some embodiments.

FIG. 27 illustrates a redistribution structure, in accordance with some other embodiments.

FIG. 28 illustrates a redistribution structure, in accordance with some other embodiments.

FIGS. 29 through 40 are cross-sectional views of intermediate steps during a process for forming a package component, in accordance with some embodiments.

FIG. 41 illustrates a system including a package component, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a redistribution structure is formed comprising dielectric layers and metallization patterns among the dielectric layers. Some of the dielectric layers are formed of molding compound materials that have a small coefficient of thermal expansion (CTE) and a large Young's Modulus. Warpage of the redistribution structure caused by shrinkage of the dielectric layers after formation may thus be reduced. Further, multiple molding compound materials may be used. For example, some dielectric layers can comprise a photoinsensitive molding compound, and other dielectric layers can comprise a photosensitive molding compound. A photosensitive molding compound is a molding compound that can be directly patterned by photolithography before curing, and a photoinsensitive molding compound is a molding compound that cannot be directly patterned by photolithography. The composition of such compounds is discussed further below. The photoinsensitive molding compound has better electrical and mechanical performance, and is particularly suitable for power and/or ground connections. The photosensitive molding compound may be formed at a lower cost, and has sufficient electrical and mechanical performance for data connections.

FIGS. 1 through 25 are cross-sectional views of intermediate steps during a process for forming a package component 50, in accordance with some embodiments. A first package region 50A is shown, in which the package component 50 is formed. It should be appreciated that multiple adjacent package regions 50A can be simultaneously formed, and a package component 50 can be formed in each of the package regions 50A.

FIG. 25 illustrates the resulting package component 50. The package component 50 includes a redistribution structure 52, an interposer 54, and a semiconductor device 56. The redistribution structure 52 is disposed between the interposer 54 and the semiconductor device 56. The semiconductor device 56 is a three-dimensional integrated circuit (3DIC) device, such as a chip-on-wafer (CoW) device, that incorporates multiple integrated circuit dies in a side-by-side manner. The interposer 54 and semiconductor device 56 are parts of a package substrate, on which the semiconductor device 56 is mounted. The package component 50 is a package implementing the 3DIC device, such as a chip-on-wafer-on-substrate (CoWoS) package.

The redistribution structure 52 is attached to the interposer 54 with conductive connectors 58, and an underfill 60 may be formed around the conductive connectors 58. The semiconductor device 56 is attached to the redistribution structure 52 with conductive connectors 62, and an underfill 64 may be formed around the conductive connectors 62. The package component 50 may also include external connectors 66, which are used to physically and electrically couple the package component 50 to external devices.

The redistribution structure 52 and interposer 54 collectively redistribute and fan-out connections from the semiconductor device 56 for electrical coupling to external connectors. The redistribution structure 52 has small conductive features for coupling to the semiconductor device 56, and the interposer 54 has large conductive features for coupling to the external connectors 66. The redistribution structure 52 is formed by photolithography techniques, which are suitable for producing small conductive features at a low cost, and the interposer 54 is formed by laser drilling techniques, which are suitable for producing large conductive features at a low cost. By combining the redistribution structure 52 and interposer 54 in a same package component 50, manufacturing costs may be reduced.

In FIG. 1, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, such that multiple packages can be formed on the carrier substrate 102 simultaneously. The release layer 104 may be formed of a polymer-based material, which may be removed along with the carrier substrate 102 from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be leveled and may have a large degree of planarity.

In FIG. 2, the redistribution structure 52 is formed on the release layer 104, and the conductive connectors 58 are formed on the redistribution structure 52. FIGS. 3 through 17 are various views of intermediate steps during a process for forming the redistribution structure 52, in accordance with some embodiments. A detailed view of a region of the redistribution structure 52 is shown. Some features in FIGS. 3 through 17 are omitted from FIG. 2 for simplicity of illustration. The redistribution structure 52 includes dielectric layers 106, 114, 122, 132, 140, 150, 160; metallization patterns 108, 116, 126, 134, 144, 154; and under-bump metallurgies (UBMs) 164. The redistribution structure 52 is shown as an example having six layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 52 by, respectively, repeating or omitting the steps and process discussed herein.

As discussed further below, the dielectric layers 114, 122, 132, 140, 150, 160 are formed of molding compound materials that each have a small coefficient of thermal expansion (CTE) and a large Young's Modulus. Wafer warpage of the redistribution structure 52 caused by shrinkage of the dielectric layers 114, 122, 132, 140, 150, 160 after formation may thus be reduced. The dielectric layers 106, 114, 122, 132, 140, 150, 160 are shown as an example. In this embodiment, the dielectric layer 106 is formed of a photosensitive polymer, the dielectric layers 114, 132 are formed of a photoinsensitive molding compound, and the dielectric layers 122, 140, 150, 160 are formed of a photosensitive molding compound. In other embodiments (discussed further below) the redistribution structure 52 may comprise other combinations of dielectric layers.

In FIG. 3, the dielectric layer 106 is deposited over the carrier substrate 102, e.g., on the release layer 104. The dielectric layer 106 may be a photosensitive polymer such as polybenzoxazole (PBO), polyimide, low temperature polyimide (LTPI), benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; the like; or a combination thereof. The dielectric layer 106 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.

In some embodiments, the dielectric layer 106 is formed of a photosensitive polymer such as LTPI, which allows the dielectric layer 106 to be formed to a small thickness T₁, such as a thickness T₁ in the range of about 7 μm to about 8 μm. A photosensitive polymer can be formed by spin coating, which can obviate the need to planarize the dielectric layer 106. Formation costs of the dielectric layer 106 may thus be reduced, but as a result, the dielectric layer 106 can have a small degree of planarity, such as less than about 50%. The dielectric layer 106 is a single continuous dielectric material layer, and so it has a small surface roughness, such as a roughness of less than about 0.1 μm.

The dielectric layer 106 has poor electrical and mechanical performance. In particular, the photosensitive polymer has a small Young's Modulus and a large CTE, both of which can result in damage to the subsequently formed metallization patterns during testing and/or operation. For example, the photosensitive polymer can have a Young's Modulus of less than 8.5 GPa, such as in the range of about 2.7 GPa to about 3.3 GPa, and can have a CTE of greater than about 20 ppm/K, such as in the range of about 50 ppm/K to about 70 ppm/K. Likewise, the photosensitive polymer has a large dielectric constant (D_(K)) and a large dissipation factor (D_(F)), which may decrease the electrical isolation between the subsequently formed metallization patterns. For example, the photosensitive polymer can have a D_(K) of greater than 2.8, such as in the range of about 3.1 to about 3.3, and a D_(F) of greater than about 0.008, such as in the range of about 0.02 to about 0.025. Despite its poor electrical and mechanical performance, the photosensitive polymer of the dielectric layer 106 is a low-cost material, and so using the photosensitive polymer for dielectric layers where electrical and mechanical performance are lesser concerns can advantageously lower manufacturing costs of the redistribution structure 52.

In FIG. 4, the metallization pattern 108 is formed on the dielectric layer 106. The metallization pattern 108 includes conductive lines 108L on and extending along the major surface of the dielectric layer 106. The metallization pattern 108 also includes conductive vias 108V on the conductive lines 108L. As an example to form the metallization pattern 108, a seed layer 110 is formed over the dielectric layer 106. In some embodiments, the seed layer 110 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 110 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 110 may be formed using, for example, physical vapor deposition (PVD) or the like. A first photoresist is then formed and patterned on the seed layer 110. The first photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the first photoresist corresponds to the conductive lines 108L. The patterning forms openings through the first photoresist to expose the seed layer 110. A conductive material 112 is then formed in the openings of the first photoresist and on the exposed portions of the seed layer 110. The conductive material 112 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 112 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The first photoresist is then removed, such as by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. A second photoresist is then formed and patterned on the seed layer 110 and conductive lines 108L. The second photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the second photoresist corresponds to the conductive vias 108V. The patterning forms openings through the second photoresist to expose the conductive lines 108L. Additional conductive material 112 is then formed in the openings of the second photoresist and on the exposed portions of the conductive lines 108L. The additional conductive material 112 may be formed by plating from the conductive lines 108L, without forming a seed layer on the conductive lines 108L. The combination of the conductive material 112 and underlying portions of the seed layer 110 form the metallization pattern 108. The second photoresist and portions of the seed layer 110 on which the conductive material 112 is not formed are removed. The second photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the second photoresist is removed, exposed portions of the seed layer 110 are removed, such as by using an acceptable etching process, such as by wet or dry etching.

In FIG. 5, the dielectric layer 114 is formed around the metallization pattern 108 and on the dielectric layer 106. After formation, the dielectric layer 114 surrounds the metallization pattern 108. In some embodiments, the dielectric layer 114 is formed of a photoinsensitive molding compound. A photoinsensitive molding compound includes a photoinsensitive resin having fillers disposed therein. Examples of photoinsensitive resins include epoxy, acrylic, or polyimide-based materials. Examples of fillers include silica or the like. The fillers have a large diameter and occupy a large portion of the dielectric layer 114. For example, the fillers can have a diameter in the range of about 1 μm to about 5 μm, and can occupy from about 70% to about 90% of the volume of the dielectric layer 114. In some embodiments, an adhesion promoter is formed on metal features such as the metallization pattern 108 before the dielectric layer 114 is formed, which can increase adhesion of the dielectric layer 114 to the metal features. Example adhesion promoters include amine-based, silane-based, thiol-based, or vinyl-based organic materials. Use of an adhesion promoter can increase adhesion of the dielectric layer 114 to metal features such as the metallization pattern 108. The photoinsensitive molding compound may be applied by compression molding, transfer molding, or the like, and may be applied in liquid or semi-liquid form and then subsequently cured. The photoinsensitive molding compound has a low curing temperature, such as a curing temperature in the range of about 160° C. to about 230° C., which can further reduce warpage of the dielectric layer 114 after curing.

The photoinsensitive molding compound has a large Young's Modulus and a small CTE, both of which can provide protection for the metallization pattern 108. For example, the photoinsensitive molding compound can have a Young's Modulus of at least about 8 GPa, such as in the range of about 8 GPa to about 10 GPa, and a CTE of less than or equal to about 20 ppm/K, such as in the range of about 15 ppm/K to about 20 ppm/K. The dielectric layer 114 has a greater Young's Modulus and a lesser CTE than the dielectric layer 106. A large Young's Modulus helps protect the metallization pattern 108 from external mechanical forces. Further, a small CTE helps protect the metallization pattern 108 from internal mechanical forces that can be generated when the metallization pattern 108 is exposed to high operating temperatures.

Because the dielectric layer 114 is formed of a photoinsensitive molding compound, it cannot be patterned by photolithography after formation. As such, the dielectric layer 114 is formed after the metallization pattern 108, and is formed over the metallization pattern 108 such that the metallization pattern 108 is buried or covered, and a planarization process is then performed on the dielectric layer 114 to expose the conductive vias 108V. Topmost surfaces of the dielectric layer 114 and conductive vias 108V are planar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP). After the planarization process, the photoinsensitive molding compound of the dielectric layer 114 has a large degree of planarity, such as a degree of planarity of greater than about 90%. Further, because the photoinsensitive molding compound contains fillers, it can have a large surface roughness. For example, after the planarization process, the dielectric layer 114 can have a surface roughness in the range of about 0.1 μm to about 0.2 μm. The dielectric layer 114 can have a greater degree of planarity and surface roughness than the dielectric layer 106.

In FIG. 6, the metallization pattern 116 is formed on the dielectric layer 114 and exposed portions of the conductive vias 108V. The metallization pattern 116 only includes conductive lines 116L, and does not have conductive vias. As discussed below, the overlying metallization pattern 126 (see FIG. 8) includes lower conductive vias 126V_(L) that will couple the conductive lines 116L, thus obviating the need for conductive vias in the metallization pattern 116 in this embodiment. As an example to form the metallization pattern 116, a seed layer 118 is formed over the dielectric layer 114 and exposed portions of the conductive vias 108V. In some embodiments, the seed layer 118 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 118 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 118 may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer 118. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 116. The patterning forms openings through the photoresist to expose the seed layer 118. A conductive material 120 is then formed in the openings of the photoresist and on the exposed portions of the seed layer 118. The conductive material 120 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 120 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material 120 and underlying portions of the seed layer 118 form the metallization pattern 116. The photoresist and portions of the seed layer 118 on which the conductive material 120 is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer 118 are removed, such as by using an acceptable etching process, such as by wet or dry etching.

The dielectric layer 114 is formed to a large thickness T₂, such as a thickness T₂ in the range of about 37 μm to about 40 μm. As noted above, the photoinsensitive molding compound of the dielectric layer 114 has a large Young's Modulus. As such, the photoinsensitive molding compound offers a large amount of mechanical support and so may be formed to a greater thickness T₂ than a nitride, oxide, or photosensitive polymer. A large thickness T₂ may allow the formation of larger conductive vias 108V and larger conductive lines 108L and 116L. In particular, the conductive vias 108V and conductive lines 108L and 116L may be formed to longer lengths and greater dimensions when the dielectric layer 114 is a molding compound. For example, the conductive lines 108L and 116L can each be formed to a large thickness T₃, such as a thickness T₃ in the range of about 7 μm to about 8 μm, and the conductive vias 108V can be formed to a large thickness T₄, such as a thickness T₄ in the range of about 30 μm to about 32 μm. Likewise, the conductive vias 108V can be formed to a large width W₁, such as a width W₁ in the range of greater than about 30 μm, such as in the range of about 27 μm to about 33 μm. Features of longer lengths and greater dimensions may be desirable for some types of connections, such as power and/or ground connections. Further, the photoinsensitive molding compound has a small D_(K) and D_(F), which may increase the electrical isolation between the conductive lines 108L and 116L. For example, the photoinsensitive molding compound can have a D_(K) of greater than 2.8, such as in the range of about 3.1 to about 3.4, and a D_(F) of less than or equal to about 0.008, such as in the range of about 0.003 to about 0.006. The dielectric layer 114 can have a smaller D_(K) and D_(F) than the dielectric layer 106. Increasing the electrical isolation between the conductive lines 108L and 116L may improve electrical performance of the power and ground connections, such as by increasing the power integrity.

In FIG. 7, the dielectric layer 122 is formed around the metallization pattern 116 and on the dielectric layer 114. After formation, the dielectric layer 122 surrounds and buries or covers the metallization pattern 116. In some embodiments, the dielectric layer 122 is formed of a photosensitive molding compound. A photosensitive molding compound includes a photosensitive resin having fillers disposed therein. Examples of photosensitive resins include epoxy and acrylic. The photosensitive resins can include photoacid generators. Examples of fillers include silica, barium sulfate (BaSO₄), or the like. Notably, the photosensitive molding compound of the dielectric layer 122 comprises a different resin and filler than the photoinsensitive molding compound of the dielectric layer 114. Further, the fillers have a small diameter and occupy a small portion of the photosensitive molding compound than the fillers of the photoinsensitive molding compound. For example, the fillers of the photosensitive molding compound can have a diameter in the range of about 0.5 μm to about 2 μm, and can occupy from about 40% to about 60% of the volume of the dielectric layer 122. In some embodiments, the photosensitive molding compound also includes an adhesion promoter, such as amine-based, silane-based, thiol-based, or vinyl-based organic material. The photosensitive molding compound may be applied by compression molding, transfer molding, or the like, and may be applied in liquid or semi-liquid form and then subsequently cured. The photosensitive molding compound has a low curing temperature, such as a curing temperature in the range of about 160° C. to about 230° C., which can further reduce warpage of the dielectric layer 122 after curing.

The photosensitive molding compound has a large Young's Modulus and a small CTE, both of which can provide protection for the metallization pattern 116. For example, the photosensitive molding compound can have a Young's Modulus in the range of about 6 GPa to about 10 GPa, such as at least 8.5 GPa, and a CTE of less than or equal to about 20 ppm/K, such as in the range of about 18 ppm/K to about 35 ppm/K. The dielectric layer 122 has a greater Young's Modulus and a lesser CTE than the dielectric layer 106. A large Young's Modulus helps protect the metallization pattern 116 from external mechanical forces. Further, a small CTE helps protect the metallization pattern 116 from internal mechanical forces that can be generated when the metallization pattern 116 is exposed to high operating temperatures.

The dielectric layer 122 is then patterned. Because the dielectric layer 122 is formed of a photosensitive molding compound, it can be patterned by photolithography after formation. Planarization of the dielectric layer 122 may thus be avoided. As such, the dielectric layer 122 is formed before the metallization pattern 126 (see FIG. 9). The patterning forms openings 124 exposing portions of the metallization pattern 116. The patterning may be by an acceptable process, such as by exposing the dielectric layer 122 to light and then developing the dielectric layer 122 after the exposure. As noted above, the photosensitive molding compound includes a photosensitive resin having fillers disposed therein. Patterning the dielectric layer 122 comprises patterning the photosensitive resin. After the photosensitive resin is patterned, it can be removed. The fillers disposed in the patterned portions of the photosensitive resin are also removed. The photosensitive resin can be cured after patterning, which reduces the photosensitivity of the dielectric layer 122.

The photosensitive molding compound of the dielectric layer 122 has a large degree of planarity, such as a degree of planarity of greater than about 90%. However, because planarization of the dielectric layer 122 may be omitted, the dielectric layer 122 may have a lesser degree of planarity than the dielectric layer 114. Further, because the photosensitive molding compound contains fillers, it can have a large surface roughness, such as a surface roughness in the range of about 0.3 μm to about 1 μm. The dielectric layer 122 has a greater surface roughness than the dielectric layer 114.

In FIG. 8, the metallization pattern 126 is formed. The metallization pattern 126 includes lower conductive vias 126V_(L) extending through the dielectric layer 122 to physically and electrically couple the metallization pattern 116. The metallization pattern 126 also includes conductive lines 126L on and extending along the major surface of the dielectric layer 122. The metallization pattern 126 further includes upper conductive vias 126V_(U) on the conductive lines 126L. As an example to form the metallization pattern 126, a seed layer 128 is formed over the dielectric layer 122 and in the openings 124 extending through the dielectric layer 122. In some embodiments, the seed layer 128 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 128 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 128 may be formed using, for example, PVD or the like. A first photoresist is then formed and patterned on the seed layer 128. The first photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the first photoresist corresponds to the conductive lines 126L and lower conductive vias 126V_(L). The patterning forms openings through the first photoresist to expose the seed layer 128. A conductive material 130 is then formed in the openings of the first photoresist and on the exposed portions of the seed layer 128. The conductive material 130 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 130 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The first photoresist is then removed, such as by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. A second photoresist is then formed and patterned on the conductive lines 126L. The second photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the second photoresist corresponds to the upper conductive vias 126V_(U). The patterning forms openings through the second photoresist to expose the conductive lines 126L. Additional conductive material 130 is then formed in the openings of the second photoresist and on the exposed portions of the conductive lines 126L. The additional conductive material 130 may be formed by plating from the conductive lines 126L, without forming a seed layer on the conductive lines 126L. The combination of the conductive material 130 and underlying portions of the seed layer 128 form the metallization pattern 126. The second photoresist and portions of the seed layer 128 on which the conductive material 130 is not formed are removed. The second photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the second photoresist is removed, exposed portions of the seed layer 128 are removed, such as by using an acceptable etching process, such as by wet or dry etching.

The dielectric layer 122 is formed to a small thickness T₅, such as a thickness T₅ in the range of about 25 μm to about 28 As noted above, the photosensitive molding compound of the dielectric layer 122 has a large Young's Modulus. As such, the photosensitive molding compound offers a large amount of mechanical support even when formed to a small thickness T₅. A small thickness T₅ may allow the formation of smaller lower conductive vias 126V_(L) and smaller conductive lines 116L and 126L. In particular, the lower conductive vias 126V_(L) may be formed to shorter lengths and smaller dimensions. For example, the lower conductive vias 126V_(L) can be formed to a small thickness T₆, such as a thickness T₆ in the range of about 18 μm to about 20 μm. Likewise, the lower conductive vias 126V_(L) can be formed to a small width W₂, such as a width W₂ in the range of about 20 μm to about 40 such as less than about 25 μm. The thickness T₆ is less than the thickness T₃, and the width W₂ is less than the width W₁. Features of shorter lengths and smaller dimensions may be desirable for some types of connections, such as data connections. Further, the photosensitive molding compound has a small D_(K) and D_(F), which may increase the electrical isolation between the conductive lines 116L and 126L. For example, the photosensitive molding compound can have a D_(K) of less than 2.8, such as in the range of about 2.3 to about 2.6, and a D_(F) of less than or equal to about 0.008, such as in the range of about 0.006 to about 0.008. The dielectric layer 122 has a smaller D_(K) and D_(F) than the dielectric layer 106. Increasing the electrical isolation between the conductive lines 116L and 126L may improve electrical performance of the data connections, such as by increasing the signal integrity.

The dielectric layer 114 (e.g., the photoinsensitive molding compound) has a larger Young's Modulus and CTE than the dielectric layer 122 (e.g., the photosensitive molding compound). Further, the dielectric layer 114 also has a smaller D_(K) and D_(F) than the dielectric layer 122. In other words, the dielectric layer 114 has better electrical and mechanical performance than the dielectric layer 122. However, the dielectric layer 122 still has sufficient electrical and mechanical performance for low-voltage signals, such as data connections. Further, as discussed above, the dielectric layer 122 can be patterned by photolithography after formation. As such, the dielectric layer 122 can be formed before the metallization pattern 126, and planarization of the dielectric layer 122 may be avoided. The dielectric layer 122 may thus be formed at a lower cost than the dielectric layer 114.

The metallization pattern 126 also has additional dimensions which are illustrated. The conductive lines 126L can be formed to a large thickness T₇, such as a thickness T₇ in the range of about 7 μm to about 8 μm. In some embodiments, the thickness T₇ is the same as the thickness T₃. Further, the upper conductive vias 126V_(U) can be formed to a large thickness T₈, such as a thickness T₈ in the range of about 30 μm to about 32 μm. In some embodiments, the thickness T₈ is the same as the thickness T₄. Further, the upper conductive vias 126V_(U) can be formed to a large width W₃, which can be in the range of about 27 μm to about 33 μm, such as greater than about 30 μm. In some embodiments, the thickness W₃ is the same as the thickness W₁.

Further, because the metallization patterns 108 and 126 are formed by different techniques, their respective conductive vias 108V and 126V_(L) form different angles with underlying features. Sidewalls of the conductive vias 108V form a first angle θ₁ with a major surface of the conductive line 108L, and sidewalls of the lower conductive via 126V_(L) form a second angle θ₂ with a major surface of the conductive line 116L. For example, the angle θ₁ can be in the range of about 80 degrees to about 90 degrees, and the angle θ₂ can be in the range of about 60 degrees to about 70 degrees. The first angle θ₁ is greater than the second angle θ₂.

In FIG. 9, the dielectric layer 132 is formed around the metallization pattern 126 and on the dielectric layer 122. After formation, the dielectric layer 132 surrounds the metallization pattern 126. The dielectric layer 132 may be formed of a similar material and in a similar manner as the dielectric layer 114. Similar to the dielectric layer 114, the dielectric layer 132 is formed over the metallization pattern 126 such that the metallization pattern 126 is buried or covered, and a planarization process is then performed on the dielectric layer 132 to expose the upper conductive vias 126V_(U). Topmost surfaces of the dielectric layer 132 and upper conductive vias 126V_(U) are planar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP). After formation, the dielectric layer 132 has a thickness T₉, such as a thickness T₉ in the range of about 37 μm to about 40 μm. In some embodiments, the thickness T₉ is the same as the thickness T₂.

In FIG. 10, the metallization pattern 134 is formed on the dielectric layer 132 and exposed portions of the upper conductive vias 126V_(U). The metallization pattern 134 only includes conductive lines 134L, and does not have conductive vias. The metallization pattern 134 may be formed of a similar material and in a similar manner as the metallization pattern 116. For example, the metallization pattern 134 can comprise a seed layer 136 and a conductive material 138 on the seed layer 136. After formation, the metallization pattern 134 has a thickness T₁₀, such as a thickness T₁₀ in the range of about 7 μm to about 8 μm. In some embodiments, the thickness T₁₀ is the same as the thickness T₃.

In FIG. 11, the dielectric layer 140 is formed around the metallization pattern 134 and on the dielectric layer 132. The dielectric layer 140 may be formed of a similar material and in a similar manner as the dielectric layer 122. The dielectric layer 140 is then patterned. The patterning forms openings 142 exposing portions of the metallization pattern 134. The patterning may be by a similar process as the process for patterning the dielectric layer 122. After formation, the dielectric layer 140 has a thickness T₁₁, such as a thickness T₁₁ in the range of about 25 μm to about 28 μm. In some embodiments, the thickness T₁₁ is the same as the thickness T₅.

In FIG. 12, the metallization pattern 144 is formed on the dielectric layer 140 and exposed portions of the metallization pattern 134. The metallization pattern 144 includes conductive vias 144V extending through the dielectric layer 140 to physically and electrically couple the metallization pattern 134. The metallization pattern 144 also includes conductive lines 144L on and extending along the major surface of the dielectric layer 140. As an example to form the metallization pattern 144, a seed layer 146 is formed over the dielectric layer 140 and in the openings 142 extending through the dielectric layer 140. In some embodiments, the seed layer 146 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 146 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 146 may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer 146. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive lines 144L and conductive vias 144V. The patterning forms openings through the photoresist to expose the seed layer 146. A conductive material 148 is then formed in the openings of the photoresist and on the exposed portions of the seed layer 146. The conductive material 148 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 148 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material 148 and underlying portions of the seed layer 146 form the metallization pattern 144. The photoresist and portions of the seed layer 146 on which the conductive material 148 is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer 146 are removed, such as by using an acceptable etching process, such as by wet or dry etching. After formation, the conductive lines 144L have a thickness T₁₂, such as a thickness T₁₂ in the range of about 7 μm to about 8 μm. In some embodiments, the thickness T₁₂ is the same as the thickness T₃. Further, the conductive vias 144V have a thickness T₁₃, such as a thickness T₁₃ in the range of about 18 μm to about 20 μm. In some embodiments, the thickness T₁₃ is the same as the thickness T₆. Further, the conductive vias 144V have a width W₄, which can be in the range of about 20 μm to about 40 μm, such as less than about 25 μm. In some embodiments, the width W₄ is the same as the width W₂.

In FIG. 13, the dielectric layer 150 is formed around the metallization pattern 144 and on the dielectric layer 140. The dielectric layer 150 may be formed of a similar material and in a similar manner as the dielectric layer 122. The dielectric layer 150 is then patterned. The patterning forms openings 152 exposing portions of the metallization pattern 144. The patterning may be by a similar process as the process for patterning the dielectric layer 122. After formation, the dielectric layer 150 has a thickness T₁₄, such as a thickness T₁₄ in the range of about 25 μm to about 28 μm. In some embodiments, the thickness T₁₄ is the same as the thickness T₅.

In FIG. 14, the metallization pattern 154 is formed on the dielectric layer 150 and the portions of the metallization pattern 144 exposed by the openings 152. The metallization pattern 154 includes conductive vias 154V extending through the dielectric layer 150 to physically and electrically couple the metallization pattern 134. The metallization pattern 154 also includes conductive lines 154L on and extending along the major surface of the dielectric layer 150. The metallization pattern 154 may be formed of a similar material and in a similar manner as the metallization pattern 144. For example, the metallization pattern 154 can comprise a seed layer 156 and a conductive material 158 on the seed layer 156. After formation, the conductive lines 154L have a thickness T₁₅, such as a thickness T₁₅ in the range of about 7 μm to about 8 μm. In some embodiments, the thickness T₁₅ is the same as the thickness T₃. Further, the conductive vias 154V have a thickness T₁₆, such as a thickness T₁₆ in the range of about 18 μm to about 20 μm. In some embodiments, the thickness T₁₆ is the same as the thickness T₆. Further, the conductive vias 154V have a width W₅, which can be in the range of about 20 μm to about 40 μm, such as less than about 25 μm. In some embodiments, the width W₅ is the same as the width W₂.

In FIG. 15, the dielectric layer 160 is formed around the metallization pattern 154 and on the dielectric layer 150. The dielectric layer 160 may be formed of a similar material and in a similar manner as the dielectric layer 122. The dielectric layer 160 is then patterned. The patterning forms openings 162 exposing portions of the metallization pattern 154. The patterning may be by a similar process as the process for patterning the dielectric layer 122. After formation, the dielectric layer 160 has a thickness T₁₇, such as a thickness T₁₇ in the range of about 25 μm to about 28 μm. In some embodiments, the thickness T₁₇ is the same as the thickness T₅.

In FIG. 16, the UBMs 164 are formed for external connection to the redistribution structure 52. The UBMs 164 include conductive vias 164V extending through the dielectric layer 160 to physically and electrically couple the metallization pattern 154. The UBMs 164 also include bumps 164B on and extending along the major surface of the dielectric layer 160. The UBMs 164 may be formed of a similar material and in a similar manner as the metallization pattern 144. For example, the UBMs 164 can comprise a seed layer 166 and a conductive material 168 on the seed layer 166. After formation, the bumps 164B have a thickness T₁₈, such as a thickness T₁₈ in the range of about 8 μm to about 10 μm. Further, the conductive vias 164V have a thickness T₁₉, such as a thickness T₁₉ in the range of about 18 μm to about 20 μm. Further, the conductive vias 154V have a width W₆, which can be in the range of about 140 μm to about 160 μm, such as greater than about 150 μm.

In FIG. 17, the conductive connectors 58 are formed on the UBMs 164. The conductive connectors 58 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors 58 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 58 are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors 58 comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In FIG. 18, the interposer 54 is attached to the redistribution structure 52. The interposer 54 may be, e.g., an organic substrate, a ceramic substrate, a silicon substrate, or the like. The conductive connectors 58 are used to attach the interposer 54 to the redistribution structure 52. Attaching the interposer 54 may include placing the interposer 54 on the conductive connectors 58 and reflowing the conductive connectors 58 to physically and electrically couple the interposer 54 to the redistribution structure 52.

Before being attached, to the redistribution structure 52 the interposer 54 may be processed according to applicable manufacturing processes to form redistribution structures in the interposer 54. For example, the interposer 54 includes a substrate core 202. The substrate core 202 may be formed of glass fiber, resin, filler, other materials, and/or combinations thereof. The substrate core 202 may be formed of organic and/or inorganic materials. In some embodiments, the substrate core 202 includes one or more passive components (not shown) embedded inside. Alternatively, the substrate core 202 may comprise other materials or components. Conductive vias 204 are formed extending through the substrate core 202. The conductive vias 204 comprise a conductive material such as copper, a copper alloy, or other conductors, and may include a barrier layer, liner, seed layer, and/or a fill material, in some embodiments. The conductive vias 204 provide vertical electrical connections from one side of the substrate core 202 to the other side of the substrate core 202. For example, some of the conductive vias 204 are coupled between conductive features at one side of the substrate core 202 and conductive features at an opposite side of the substrate core 202. Holes for the conductive vias 204 may be formed using a drilling process, photolithography techniques, a laser process, or other methods, as examples, and the holes of the conductive vias 204 are then filled with conductive material. In some embodiments, the conductive vias 204 are hollow conductive through vias having centers that are filled with an insulating material. Redistribution structures 206A and 206B are formed on opposing sides of the substrate core 202. The redistribution structures 206A and 206B are electrically coupled by the conductive vias 204, and fan-out electrical signals. The redistribution structures 206A and 206B each include dielectric layers and metallization patterns. Each respective metallization pattern has line portions on and extend along the major surface of a respective dielectric layer, and has via portions extending through the respective dielectric layer. The redistribution structures 206A and 206B each, respectively, include UBMs 208A and 208B for external connection, and solder resists 210A and 210B protecting the features of the redistribution structures 206A and 206B. The redistribution structure 206A is attached to the redistribution structure 52 by the UBMs 208A.

In FIG. 19, an underfill 60 may be formed surrounding the conductive connectors 58. The underfill 60 may reduce stress and protect the joints resulting from the reflowing of the conductive connectors 58. The underfill 60 may be formed by a capillary flow process after the interposer 54 is attached to the redistribution structure 52, or may be formed by a suitable deposition method before the interposer 54 is attached to the redistribution structure 52. The underfill 60 may be formed along sidewalls of the interposer 54.

In FIG. 20, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate 102 from the redistribution structure 52, e.g., from the dielectric layer 106. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer 104 so that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 can be removed. The structure is then flipped over and placed on a tape.

In FIG. 21, openings 170 are formed in the dielectric layer 106, exposing the metallization pattern 108. The openings 170 may be formed by a drilling process such as laser drilling, mechanical drilling, or the like.

In FIG. 22, the conductive connectors 62 are formed in the openings 170, physically and electrically coupled to the exposed metallization pattern 108. The conductive connectors 62 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, or the like. The conductive connectors 62 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 62 are formed by initially forming a layer of reflowable material in the openings 170 through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of reflowable material has been formed in the openings 170, a reflow may be performed in order to shape the material into the desired bump shapes.

In FIG. 23, the semiconductor device 56 is attached to the redistribution structure 52, opposite the interposer 54. In some embodiments, the semiconductor device 56 is a package that includes one or more integrated circuit dies for forming a computing system. In the embodiment shown, the semiconductor device 56 includes a logic die 302 and memory devices 304. The logic die 302 may be, e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, or the like. The memory devices 304 may be, e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, hybrid memory cube (HMC) devices, high bandwidth memory (HBM) devices, or the like. The logic die 302 and memory devices 304 are attached to and interconnected by a redistribution structure 306. The redistribution structure 306 may be, e.g., an interposer or the like, and has connectors 308 for external connection. An encapsulant 310 may be formed over the redistribution structure 306 and around the logic die 302 and memory devices 304, thereby protecting the various components of the semiconductor device 56.

The conductive connectors 62 are used to attach the connectors 308 of the semiconductor device 56 to the metallization pattern 108 of the redistribution structure 52. Attaching the semiconductor device 56 may include placing the semiconductor device 56 on the conductive connectors 62 and reflowing the conductive connectors 62 to physically and electrically couple the semiconductor device 56 to the redistribution structure 52.

In some embodiments, an underfill 64 is formed surrounding the conductive connectors 62. The underfill 64 may reduce stress and protect the joints resulting from the reflowing of the conductive connectors 62. The underfill 64 may be formed by a capillary flow process after the semiconductor device 56 is attached to the redistribution structure 52, or may be formed by a suitable deposition method before the semiconductor device 56 is attached to the redistribution structure 52.

In FIG. 24, the external connectors 66 are formed on the UBMs 208B. The external connectors 66 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, or the like. The external connectors 66 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the external connectors 66 are formed by initially forming a layer of reflowable material on the UBMs 208B through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of reflowable material has been formed on the UBMs 208B, a reflow may be performed in order to shape the material into the desired bump shapes.

In FIG. 25, a singulation process is performed by sawing along scribe line regions, e.g., around the first package region 50A. The sawing singulates the first package region 50A from adjacent package regions. The resulting, singulated package component 50 is from the first package region 50A.

FIG. 26 illustrates a system including a package component 50, in accordance with some embodiments. In this embodiment, the package component 50 is mounted to a package substrate 312 using the external connectors 66. The package substrate 312 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the package substrate 312 may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate 312 is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for package substrate 312.

The package substrate 312 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The devices may be formed using any suitable methods.

The package substrate 312 may also include metallization layers and vias (not shown) and bond pads 314 over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 312 is substantially free of active and passive devices.

In some embodiments, the external connectors 66 are reflowed to attach the package component 50 to the bond pads 314. The external connectors 66 electrically and/or physically couple the package substrate 312, including metallization layers in the package substrate 312, to the package component 50. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may be attached to the package component 50 (e.g., bonded to the bond pads 314) prior to mounting on the package substrate 312. In such embodiments, the passive devices may be bonded to a same surface of the package component 50 as the external connectors 66.

The external connectors 66 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the package component 50 is attached to the package substrate 312. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the external connectors 66. In some embodiments, an underfill (not shown) may be formed between the package component 50 and the package substrate 312, surrounding the external connectors 66. The underfill may be formed by a capillary flow process after the package component 50 is attached or may be formed by a suitable deposition method before the package component 50 is attached.

FIG. 27 illustrates a redistribution structure 52, in accordance with some other embodiments. In this embodiment, the redistribution structure 52 includes alternating layers of photosensitive and photoinsensitive materials. In particular, the dielectric layer 106 is formed of a photosensitive polymer, the dielectric layers 114, 132, 150 are formed of a photoinsensitive molding compound, and the dielectric layers 122, 140, 160 are formed of a photosensitive molding compound. The metallization pattern 108 includes conductive lines 108L and conductive vias 108V. The metallization patterns 116, 134, 154 each, respectively, include conductive lines 116L, 134L, 154L and omit conductive vias. In each place where a photoinsensitive molding compound is formed on a photosensitive molding compound, the corresponding metallization pattern includes a lower conductive via extending through the photosensitive molding compound and an upper conductive via extending through the photoinsensitive molding compound. For example, the metallization pattern 126 includes a lower conductive via 126V_(L) extending through the dielectric layer 122, a conductive line 126L extending along the dielectric layer 122, and an upper conductive via 126V_(U) extending through the dielectric layer 132. Likewise, the metallization pattern 144 includes a lower conductive via 144V_(L) extending through the dielectric layer 140, a conductive line 144L extending along the dielectric layer 140, and an upper conductive via 144V_(U) extending through the dielectric layer 150.

FIG. 28 illustrates a redistribution structure 52, in accordance with some other embodiments. In this embodiment, all of the layers of the redistribution structure 52 are a photosensitive material. In particular, the dielectric layer 106 is formed of a photosensitive polymer, and the dielectric layers 114, 122, 132, 140, 150, 160 are formed of a photosensitive molding compound. The metallization pattern 108 includes conductive lines 108L and omits conductive vias. The metallization patterns 116, 126, 134, 144, 154 each, respectively, include conductive lines 116L, 126L, 134L, 144L, 154L extending along, respectively, the dielectric layers 114, 122, 132, 140, 150. Further, the metallization patterns 116, 126, 134, 144, 154 each, respectively, include conductive vias 116V, 126V, 134V, 144V, 154V extending through, respectively, the dielectric layers 114, 122, 132, 140, 150.

FIGS. 29 through 40 illustrate cross-sectional views of intermediate steps during a process for forming a package component 400, in accordance with some embodiments. A first package region 400A is shown, in which the package component 400 is formed. It should be appreciated that multiple adjacent package regions 400A can be simultaneously formed, and a package component 400 can be formed in each of the package regions 400A. The package component 400 may be referred to as an integrated fan-out (InFO) package.

In FIG. 29, a carrier substrate 402 is provided, and a release layer 404 is formed on the carrier substrate 402. The carrier substrate 402 may be similar to the carrier substrate 102, and the release layer 404 may be similar to the release layer 104.

A back-side redistribution structure 406 may be formed on the release layer 404. In the embodiment shown, the back-side redistribution structure 406 includes a dielectric layer 408, a metallization pattern 410 (sometimes referred to as redistribution layers or redistribution lines), and a dielectric layer 412. The back-side redistribution structure 406 is optional. In some embodiments, a dielectric layer without metallization patterns is formed on the release layer 404 in lieu of the back-side redistribution structure 406.

The dielectric layer 408 may be formed on the release layer 404. The bottom surface of the dielectric layer 408 may be in contact with the top surface of the release layer 404. In some embodiments, the dielectric layer 408 is formed of a photosensitive polymer, such as polybenzoxazole (PBO), polyimide, low temperature polyimide (LTPI), benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 408 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 408 may be formed by spin coating, lamination, chemical vapor deposition (CVD), or the like.

The metallization pattern 410 may be formed on the dielectric layer 408. As an example to form metallization pattern 410, a seed layer is formed over the dielectric layer 408. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 410. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern 410.

The dielectric layer 412 may be formed on the metallization pattern 410 and the dielectric layer 408. In some embodiments, the dielectric layer 412 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, low temperature polyimide (LTPI), BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer 412 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 412 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

It should be appreciated that the back-side redistribution structure 406 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically couple the various conductive lines.

Next, through vias 414 are formed extending through and away from the topmost dielectric layer of the back-side redistribution structure 406 (e.g., the dielectric layer 412). The through vias 414 are optional, and as discussed further below, may be omitted. For example, the through vias 414 may (or may not) be omitted in embodiments where the back-side redistribution structure 406 is omitted. As an example to form the through vias 414, the dielectric layer 412 can be patterned to form openings exposing portions of the metallization pattern 410. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer 412 to light when the dielectric layer 412 is a photosensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer 412 is a photosensitive material, the dielectric layer 412 can be developed after the exposure. A seed layer is then formed over the dielectric layer 412 and portions of the metallization pattern 410 exposed by the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to conductive vias. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the through vias 414.

In FIG. 30, integrated circuit dies 416 are adhered to the dielectric layer 412 by an adhesive 418. A desired type and quantity of integrated circuit dies 416 are adhered in the first package region 400A. Each integrated circuit die 416 may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In the embodiment shown, multiple integrated circuit dies 416, such as a first integrated circuit die 416A and a second integrated circuit die 416B, are adhered adjacent one another in the first package region 400A. In some embodiments, the first integrated circuit die 416A can be a logic die and the second integrated circuit die 416B can be a memory die. The adhesive 418 is on back-sides of the integrated circuit dies 416 and adheres the integrated circuit dies 416 to the back-side redistribution structure 406, such as to the dielectric layer 412. The adhesive 418 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 418 may be applied to back-sides of the integrated circuit dies 416 or may be applied over the surface of the carrier substrate 402. For example, the adhesive 418 may be applied to the back-sides of the integrated circuit dies 416 before the integrated circuit dies 416 are singulated.

Before adhesion to the dielectric layer 412, each integrated circuit die 416 may be processed according to applicable manufacturing processes to form integrated circuits. For example, each integrated circuit die 416 includes a semiconductor substrate 420, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 420 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate 420 has an active surface (e.g., the surface facing upwards in FIG. 30), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards in FIG. 30), sometimes called a back side. Devices may be formed at the front surface of the semiconductor substrate 420. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 422 is over the semiconductor substrate 420, and interconnects the devices to form an integrated circuit. The interconnect structure 422 may be formed by, for example, metallization patterns in dielectric layers on the semiconductor substrate 420. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure 422 are electrically coupled to the devices of the semiconductor substrate 420.

The integrated circuit die 416 further includes pads 424, such as aluminum pads, to which external connections are made. The pads 424 are on the active side of the integrated circuit die 416, such as in and/or on the interconnect structure 422. One or more passivation films 426 are on the integrated circuit die 416, such as on portions of the interconnect structure 422 and pads 424. Openings extend through the passivation films 426 to the pads 424. Die connectors 428, such as conductive pillars (for example, formed of a metal such as copper), extend through the openings in the passivation films 426 and are physically and electrically coupled to respective ones of the pads 424. The die connectors 428 may be formed by, for example, plating, or the like. The die connectors 428 electrically couple the respective integrated circuits of the integrated circuit die 416.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads 424. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die 416. CP testing may be performed on the integrated circuit die 416 to ascertain whether the integrated circuit die 416 is a known good die (KGD). Thus, only integrated circuit dies 416, which are KGDs, undergo subsequent processing are packaged, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layer 430 may (or may not) be on the active side of the integrated circuit die 416, such as on the passivation films 426 and the die connectors 428. The dielectric layer 430 laterally encapsulates the die connectors 428, and the dielectric layer 430 is laterally coterminous with the integrated circuit die 416. Initially, the dielectric layer 430 may bury the die connectors 428, such that the topmost surface of the dielectric layer 430 is above the topmost surfaces of the die connectors 428. In some embodiments where solder regions are disposed on the die connectors 428, the dielectric layer 430 may also bury the solder regions. Alternatively, the solder regions may be removed prior to forming the dielectric layer 430.

The dielectric layer 430 may be a polymer such as polybenzoxazole (PBO), polyimide, low temperature polyimide (LTPI), benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; the like, or a combination thereof. The dielectric layer 430 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors 428 are exposed through the dielectric layer 430 during formation of the integrated circuit die 416. In some embodiments, the die connectors 428 remain buried and are exposed during a subsequent process for packaging the integrated circuit die 416. Exposing the die connectors 428 may remove any solder regions that may be present on the die connectors 428.

In FIG. 31, an encapsulant 432 is formed on and around the various components. After formation, the encapsulant 432 encapsulates the through vias 414 and integrated circuit dies 416. The encapsulant 432 may be a molding compound, epoxy, or the like. The encapsulant 432 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 402 such that the through vias 414 and/or the integrated circuit dies 416 are buried or covered. The encapsulant 432 is further formed in gap regions between the integrated circuit dies 416, if present. The encapsulant 432 may be applied in liquid or semi-liquid form and then subsequently cured.

A planarization process may be performed on the encapsulant 432 to expose the through vias 414 and the die connectors 428. The planarization process may remove material of the through vias 414, die connectors 428, and/or dielectric layer 430 until the die connectors 428 and through vias 414 are exposed. Top surfaces of the through vias 414, die connectors 428, dielectric layer 430, and encapsulant 432 are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like.

In FIG. 32, a redistribution structure 434 is formed on the release layer 104, and external connectors 436 are formed on to the redistribution structure 434. FIGS. 33 through 39 are various views of intermediate steps during a process for forming the redistribution structure 434, in accordance with some embodiments. A detailed view of a region of the redistribution structure 434 is shown. Some features in FIGS. 33 through 39 are omitted from FIG. 32 for simplicity of illustration. The redistribution structure 434 includes dielectric layers 438, 448, 456, 464, 472, 480, 490; metallization patterns 442, 450, 458, 466, 474, 484; and UBMs 492. The redistribution structure 434 is shown as an example having six layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 434 by, respectively, repeating or omitting the steps and process discussed herein.

In FIG. 33, the dielectric layer 438 is deposited on the through vias 414, die connectors 428, and encapsulant 432. In some embodiments, the dielectric layer 438 is formed of a photosensitive material such as PBO, polyimide, low temperature polyimide (LTPI), BCB, or the like, which may be patterned using a lithography mask. The dielectric layer 438 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 438 is then patterned. The patterning forms openings 440 exposing portions of the through vias 414 and the die connectors 428. The patterning may be by an acceptable process, such as by exposing the dielectric layer 438 to light when the dielectric layer 438 is a photosensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer 438 is a photosensitive material, the dielectric layer 438 can be developed after the exposure.

In FIG. 34, the metallization pattern 442 is formed. The metallization pattern 442 includes conductive lines 442L on and extending along the major surface of the dielectric layer 438. The metallization pattern 442 also includes conductive vias 442V extending through the dielectric layer 438. As an example to form the metallization pattern 442, a seed layer 444 is formed over the dielectric layer 438 and in the openings 440 extending through the dielectric layer 438. In some embodiments, the seed layer 444 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 444 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 444 may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer 444. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 442. The patterning forms openings through the photoresist to expose the seed layer 444. A conductive material 446 is then formed in the openings of the photoresist and on the exposed portions of the seed layer 444. The conductive material 446 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 446 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material 446 and underlying portions of the seed layer 444 form the metallization pattern 442. The photoresist and portions of the seed layer 444 on which the conductive material 446 is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer 444 are removed, such as by using an acceptable etching process, such as by wet or dry etching.

In FIG. 35, the dielectric layer 448 is deposited on the metallization pattern 442 and dielectric layer 438. The dielectric layer 448 may be formed of a similar material and in a similar manner as the dielectric layer 438. The dielectric layer 448 is then patterned with openings exposing portions of the metallization pattern 442. The metallization pattern 450 is then formed. The metallization pattern 450 includes conductive lines 450L on and extending along the major surface of the dielectric layer 448. The metallization pattern 450 also includes conductive vias 450V extending through the openings in the dielectric layer 448. The metallization pattern 450 may be formed of a similar material and in a similar manner as the metallization pattern 442. For example, the metallization pattern 450 can comprise a seed layer 452 and a conductive material 454 on the seed layer 452.

The dielectric layer 456 is deposited on the metallization pattern 450 and dielectric layer 448. The dielectric layer 456 may be formed of a similar material and in a similar manner as the dielectric layer 438. The dielectric layer 456 is then patterned with openings exposing portions of the metallization pattern 450. The metallization pattern 458 is then formed. The metallization pattern 458 includes conductive lines 458L on and extending along the major surface of the dielectric layer 456. The metallization pattern 458 also includes conductive vias 458V extending through the openings in the dielectric layer 456. The metallization pattern 458 may be formed of a similar material and in a similar manner as the metallization pattern 442. For example, the metallization pattern 458 can comprise a seed layer 460 and a conductive material 462 on the seed layer 460.

The dielectric layer 464 is deposited on the metallization pattern 458 and dielectric layer 456. The dielectric layer 464 may be formed of a similar material and in a similar manner as the dielectric layer 438. The dielectric layer 464 is then patterned with openings exposing portions of the metallization pattern 458. The metallization pattern 466 is then formed. The metallization pattern 466 includes conductive lines 466L on and extending along the major surface of the dielectric layer 464. The metallization pattern 466 also includes conductive vias 466V extending through the openings in the dielectric layer 464. The metallization pattern 466 may be formed of a similar material and in a similar manner as the metallization pattern 442. For example, the metallization pattern 466 can comprise a seed layer 468 and a conductive material 470 on the seed layer 468.

The dielectric layer 472 is deposited on the metallization pattern 466 and dielectric layer 464. The dielectric layer 472 may be formed of a similar material and in a similar manner as the dielectric layer 438. The dielectric layer 472 is then patterned with openings exposing portions of the metallization pattern 466. The metallization pattern 474 is then formed. The metallization pattern 474 includes conductive lines 474L on and extending along the major surface of the dielectric layer 472. The metallization pattern 474 also includes conductive vias 474V extending through the openings in the dielectric layer 472. The metallization pattern 474 may be formed of a similar material and in a similar manner as the metallization pattern 442. For example, the metallization pattern 474 can comprise a seed layer 476 and a conductive material 478 on the seed layer 476.

In FIG. 36, the dielectric layer 480 is formed around the metallization pattern 474 and on the dielectric layer 472. The dielectric layer 480 is formed of a photosensitive molding compound, which is similar to the photosensitive molding compound of the dielectric layer 122 (see FIG. 11). Higher levels of the redistribution structure 434 have large dimensions, e.g., large thicknesses, and as discussed above, the photosensitive molding compound can be formed to large thicknesses at a low cost. The dielectric layer 480 is then patterned. The patterning forms openings 482 exposing portions of the metallization pattern 474. The patterning may be by a similar process as the process for patterning the dielectric layer 122 (see FIG. 11).

In FIG. 37, the metallization pattern 484 is formed. The metallization pattern 484 includes conductive lines 484L on and extending along the major surface of the dielectric layer 480. The metallization pattern 484 also includes conductive vias 484V extending through the openings 482 in the dielectric layer 480. The metallization pattern 484 may be formed of a similar material and in a similar manner as the metallization pattern 442. For example, the metallization pattern 484 can comprise a seed layer 486 and a conductive material 488 on the seed layer 486.

Because the metallization patterns 442 and 484 are formed by different techniques, their respective conductive vias 442V and 484V form different angles with underlying features. Sidewalls of the conductive vias 442V form a third angle θ₃ with a major surface of the encapsulant 432, and sidewalls of the conductive via 484V form a fourth angle θ₄ with a major surface of the conductive line 474L. For example, the angle θ₃ can be in the range of about 70 degrees to about 80 degrees, and the angle θ₄ can be in the range of about 60 degrees to about 70 degrees. The third angle θ₃ is greater than the fourth angle θ₄.

In FIG. 38, the dielectric layer 490 is deposited on the metallization pattern 484 and dielectric layer 480. The dielectric layer 490 may be formed of a similar material and in a similar manner as the dielectric layer 480. The dielectric layer 490 is then patterned with openings exposing portions of the metallization pattern 484. The UBMs 492 are then formed. The UBMs 492 include bumps 492B on and extending along the major surface of the dielectric layer 490. The UBMs 492 also include conductive vias 492V extending through the openings in the dielectric layer 490. The UBMs 492 may be formed of a similar material and in a similar manner as the metallization pattern 484. For example, the UBMs 492 can comprise a seed layer 494 and a conductive material 496 on the seed layer 494.

In FIG. 39, the external connectors 436 are formed on the UBMs 492. The external connectors 436 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The external connectors 436 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the external connectors 436 are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the external connectors 436 comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In FIG. 40, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate 402 from the back-side redistribution structure 406, e.g., the dielectric layer 408. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer 404 so that the release layer 404 decomposes under the heat of the light and the carrier substrate 402 can be removed. A singulation process is then performed by sawing along scribe line regions, e.g., around the first package region 400A. The sawing singulates the first package region 400A from adjacent package regions. The resulting, singulated package component 400 is from the first package region 400A.

FIG. 41 illustrates a system including a package component 400, in accordance with some embodiments. In this embodiment, the package component 400 is mounted to a package substrate 500 using the external connectors 436. The package substrate 500 can be similar to the package substrate 312, e.g., can include bond pads 502 to which the external connectors 436 are bonded.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

Embodiments may achieve advantages. Forming a redistribution structure from a combination of photoinsensitive molding compound layers and photosensitive molding compound layers allows layers with power and/or ground connections to have high electrical and mechanical performance, and allows layers with data connections to be formed at a lower cost. Further, forming a redistribution structure from a combination of photosensitive polymer layers and photosensitive molding compound layers allows upper layers of the redistribution structure to have a greater electrical and mechanical performance than lower layers, while keeping manufacturing costs low.

In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first metallization pattern including a first conductive line and a first conductive via, the first conductive line being electrically coupled to the semiconductor device, the first conductive via being disposed on the first conductive line; a first dielectric layer surrounding the first metallization pattern, surfaces of the first dielectric layer and the first conductive via being planar, the first dielectric layer including a first molding compound; a second metallization pattern including a second conductive line extending along a major surface of the first dielectric layer; a second dielectric layer disposed around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a second molding compound, the second molding compound being different from the first molding compound; and a third metallization pattern including a third conductive line and a second conductive via, the third conductive line extending along a major surface of the second dielectric layer, the second conductive via extending through the second dielectric layer to electrically couple the second metallization pattern.

In some embodiments of the device, a first sidewall of the first conductive via forms a first angle with a major surface of the first conductive line, and a second sidewall of the second conductive via forms a second angle with a major surface of the second conductive line, the first angle being greater than the second angle. In some embodiments of the device, the first molding compound includes a first resin and first fillers disposed in the first resin, and the second molding compound includes a second re sin and second fillers disposed in the second resin, the first resin being different from the second resin, the first fillers being different from the second fillers. In some embodiments of the device, the first fillers occupy a first volume of the first molding compound, the second fillers occupy a second volume of the second molding compound, and the first volume is greater than the second volume. In some embodiments of the device, the first fillers are silica and the second fillers are barium sulfate. In some embodiments of the device, the first molding compound has a greater Young's Modulus than the second molding compound, the first molding compound has a lesser coefficient of thermal expansion than the second molding compound, the first molding compound has a lesser dielectric constant than the second molding compound, and the first molding compound has a lesser dissipation factor than the second molding compound. In some embodiments of the device, the third metallization pattern further includes a third conductive via disposed on the third conductive line, and the redistribution structure further includes a third dielectric layer surrounding the third metallization pattern, surfaces of the third dielectric layer and the third conductive via being planar, the third dielectric layer including the first molding compound. In some embodiments of the device, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

In an embodiment, a device includes: an integrated circuit die; an encapsulant surrounding the integrated circuit die, surfaces of the encapsulant and the integrated circuit die being planar; a first dielectric layer over the encapsulant and the integrated circuit die, the first dielectric layer including a polymer material; a first metallization pattern including a first conductive line and a first conductive via, the first conductive line extending along a major surface of the first dielectric layer, the first conductive via extending through the first dielectric layer to electrically couple the integrated circuit die; a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including a molding material, the molding material being different from the polymer material; and a second metallization pattern including a second conductive line and a second conductive via, the second conductive line extending along a major surface of the second dielectric layer, the second conductive via extending through the second dielectric layer to electrically couple the first conductive line.

In some embodiments, the device further includes: a through via extending through the encapsulant, the first dielectric layer being over the through via, the first metallization pattern being electrically coupled to the through via. In some embodiments of the device, a first sidewall of the first conductive via forms a first angle with a major surface of the encapsulant, and a second sidewall of the second conductive via forms a second angle with a major surface of the first conductive line, the first angle being greater than the second angle. In some embodiments of the device, the polymer material is low temperature polyimide, the low temperature polyimide being free from fillers. In some embodiments of the device, the molding material includes: a resin; and fillers disposed in the resin. In some embodiments of the device, the resin is epoxy or acrylic. In some embodiments of the device, the fillers are silica or barium sulfate. In some embodiments of the device, fillers have a diameter in a range of 0.5 μm to 2 μm, and occupy from 40% to 60% of the volume of the second dielectric layer.

In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

In some embodiments of the method, the photoinsensitive molding compound includes a photoinsensitive resin and first fillers disposed in the photoinsensitive resin, the photosensitive molding compound includes a photosensitive resin and second fillers disposed in the photosensitive resin, the second fillers having smaller diameters than the first fillers. In some embodiments of the method, patterning the second dielectric layer includes: exposing the photosensitive resin to light; developing the photosensitive resin; and removing the second fillers from the openings after developing the photosensitive resin. In some embodiments, the method further includes: dispensing a third dielectric layer around the third metallization pattern and on the second dielectric layer, the third dielectric layer including the photoinsensitive molding compound; and planarizing the third dielectric layer such that surfaces of the third dielectric layer and the third metallization pattern are planar.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A device comprising: a semiconductor device; and a redistribution structure comprising: a first metallization pattern comprising a first conductive line and a first conductive via, the first conductive line being electrically coupled to the semiconductor device, the first conductive via being disposed on the first conductive line; a first dielectric layer surrounding the first metallization pattern, surfaces of the first dielectric layer and the first conductive via being planar, the first dielectric layer comprising a first molding compound; a second metallization pattern comprising a second conductive line extending along a major surface of the first dielectric layer, wherein the second metallization pattern is in direct contact with the first dielectric layer; a second dielectric layer disposed around the second metallization pattern and on the first dielectric layer, the second dielectric layer comprising a second molding compound, the second molding compound being different from the first molding compound; and a third metallization pattern comprising a third conductive line and a second conductive via, the third conductive line extending along a major surface of the second dielectric layer, the second conductive via extending through the second dielectric layer to electrically couple the second metallization pattern.
 2. The device of claim 1, wherein a first sidewall of the first conductive via forms a first angle with a major surface of the first conductive line, and wherein a second sidewall of the second conductive via forms a second angle with a major surface of the second conductive line, the first angle being greater than the second angle.
 3. The device of claim 1, wherein the first molding compound comprises a first resin and first fillers disposed in the first resin, wherein the second molding compound comprises a second resin and second fillers disposed in the second resin, the first resin being different from the second resin, the first fillers being different from the second fillers.
 4. The device of claim 3, wherein the first fillers occupy a first volume of the first molding compound, wherein the second fillers occupy a second volume of the second molding compound, and wherein the first volume is greater than the second volume.
 5. The device of claim 3, wherein the first fillers are silica and the second fillers are barium sulfate.
 6. The device of claim 1, wherein the first molding compound has a greater Young's Modulus than the second molding compound, wherein the first molding compound has a lesser coefficient of thermal expansion than the second molding compound, wherein the first molding compound has a lesser dielectric constant than the second molding compound, and wherein the first molding compound has a lesser dissipation factor than the second molding compound.
 7. The device of claim 1, wherein the third metallization pattern further comprises a third conductive via disposed on the third conductive line, and wherein the redistribution structure further comprises a third dielectric layer surrounding the third metallization pattern, surfaces of the third dielectric layer and the third conductive via being planar, the third dielectric layer comprising the first molding compound.
 8. The device of claim 1, wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.
 9. A device comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die, surfaces of the encapsulant and the integrated circuit die being planar; a first dielectric layer over the encapsulant and the integrated circuit die, the first dielectric layer comprising a polymer material; a first metallization pattern comprising a first conductive line and a first conductive via, the first conductive line extending along a major surface of the first dielectric layer, the first conductive via extending through the first dielectric layer to electrically couple the integrated circuit die; a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer comprising a molding material, the molding material being different from the polymer material; and a second metallization pattern comprising a second conductive line and a second conductive via, the second conductive line extending along a major surface of the second dielectric layer, the second conductive via extending through the second dielectric layer to electrically couple the first conductive line.
 10. The device of claim 9 further comprising: a through via extending through the encapsulant, the first dielectric layer being over the through via, the first metallization pattern being electrically coupled to the through via.
 11. The device of claim 9, wherein a first sidewall of the first conductive via forms a first angle with a major surface of the encapsulant, and wherein a second sidewall of the second conductive via forms a second angle with a major surface of the first conductive line, the first angle being greater than the second angle.
 12. The device of claim 9, wherein the polymer material is low temperature polyimide, the low temperature polyimide being free from fillers.
 13. The device of claim 9, wherein the molding material comprises: a resin; and fillers disposed in the resin.
 14. The device of claim 13, wherein the resin is epoxy or acrylic.
 15. The device of claim 13, wherein the fillers are silica or barium sulfate.
 16. The device of claim 13, wherein fillers have a diameter in a range of 0.5 μm to 2 μm, and occupy from 40% to 60% of the volume of the second dielectric layer.
 17. A method comprising: encapsulating an integrated circuit die with an encapsulant, surfaces of the encapsulant and the integrated circuit die being planar; depositing a polymer material over the encapsulant and the integrated circuit die; forming a first metallization pattern comprising a first conductive line and a first conductive via, the first conductive line extending along a major surface of the polymer material, the first conductive via extending through the polymer material to electrically couple the integrated circuit die; forming a photosensitive molding compound over the first metallization pattern and the polymer material, the photosensitive molding compound different from the polymer material; and forming a second metallization pattern comprising a second conductive line and a second conductive via, the second conductive line extending along a major surface of the photosensitive molding compound, the second conductive via extending through the photosensitive molding compound to electrically couple the first conductive line.
 18. The method of claim 17 further comprising: placing the integrated circuit die adjacent to a through via, the encapsulant surrounding the through via and the integrated circuit die, the polymer material deposited over the through via, the first metallization pattern electrically coupled to the through via.
 19. The method of claim 17, wherein a first sidewall of the first conductive via forms a first angle with a major surface of the encapsulant, and wherein a second sidewall of the second conductive via forms a second angle with a major surface of the first conductive line, the first angle greater than the second angle.
 20. The method of claim 17, wherein depositing the polymer material comprises: depositing a low temperature polyimide, the low temperature polyimide free from fillers. 